Responsibilities:
● The team is responsible for the complete implementation lifecycle, from logic synthesis of design into technology specific mapping to tape out and post-silicon support.
● The responsibility of the position involves developing synthesis constraints to meet performance,power and area targets and logic equivalence check of RTL with mapped design.
● Linting of RTL code to ensure quality of design.
● Detailed analysis of asynchronous clock domain crossings to ensure proper synchronization.
● Verification of power domain crossings for correct implementation of level shifters and isolation.
● Supporting functional ECO design changes,identifying logic changes including formal equivalency check.
● Actively work with the design team to resolve implementation and timing issues.
● Involve in developing script automation to improve implementation efficiency.
● Reviewing existing engineering criteria for similar products.
● Conducting quality control inspections.
Qualifications:
● Bachelor's Degree in Science,Engineering,or related field and 12+ years of ASIC implementation or related work experience Minimum 8 years of synthesis experience.
● Experience in VHDL, Verilog and/or System-Verilog and scripting languages.
● Experience in advance process nodes 16nm and below.
● Experience with logic libraries and PDKs, with different track libraries and multi-voltage standard cells (GO1/GO2).
● Experience with static timing analysis, CDC and RDC checks.
● Experience with UPF multi-power domain designs and verification of power domain crossings.
● Exposure to multiple successful tape-outs from conception to post silicon debug to production release.
● Knowledge of design processes and quality control procedures.
● Knowledge of wafer manufacturing procedures.
● Excellent analytical and troubleshooting skills.
● A good eye and attention to detail.
● Advanced verbal and written communication skills.
Work location: Shanghai
Contact us
021-061273702
info@istarchip.com